A recent board I designed used an Altera Cyclone VI FPGA. This FPGA’s configuration scheme is set by the value presented to the part’s MSEL lines.
When I first tried to bring up my board, I had these lines tied in a way that would have been defined for the GX version of this part, but not the E version that I was using. When I tried to connect by JTAG, I could observe lots of traffic on the JTAG lines, but the utility gave me the conf_done failed to go high message, which from what I can tell means almost anything that prevents communication with the FPGA. The FPGA held various I/O lines high or low without apparent order. Within a single bank, some lines would be weakly pulled up, some lines would be high or low, and some would be at intermediate values. I put resistors on the lines that were high or low and found a 100 ohm resistor would usually pull them most of the way up or down but not all the way. The way so many lines were pulled up or down made me think that I had a footprint error, major soldering defects, or some kind of fabrication error allowing planes to touch some of the signal vias.
One of the lines being pulled low was my processor’s reset line. (Maybe it was a bad idea to connect it to the FPGA, but I had spare pins so I went to town connecting nets that I didn’t plan to use on the FPGA.) I couldn’t cut the line because it ran on an internal layer the whole way. I ended up removing the processor, thinking some kind of error with the processor was causing its reset line to be held low. I was disappointed to discover that the line was still being pulled low just as strong. I was considering removing the FPGA too when I discovered the MSEL error.
After fixing MSEL everything amazingly worked. The MSEL line is the only jumper wire on the whole board now.
The FPGA datasheet says the MSEL lines must be tied directly (not through resistors or driven by another device) to V[CCA] (not to the I/O voltage). After this, I will always follow any rules related to MSEL lines to the letter.